The present invention relates to a circuit technique for correcting an offset voltage of a differential amplifier having a pair of differential transistors, as well as to a circuit technique for correcting an offset voltage of a class D amplifier.
The differential amplifier generally has an offset voltage. Even when two input signals have the same voltage (i.e., a difference between the two input signals is zero), an output signal assumes a value differing from an ideal value. The reason for this is that each of the transistors constituting the differential amplifier has various factors of property variations attributable to variations in a threshold value, or the like.
A known related-art technique for correcting such an offset voltage of the differential amplifier is an offset voltage correction circuit which causes an electric current to flow into one of a differential pair of transistors constituting the differential amplifier, thereby correcting the offset voltage (see JP-A-8-256025).
FIG. 10 is a circuit diagram of a differential amplifier having the above related-art offset voltage correction circuit. In the drawing, reference numerals 500 and 501 designate NMOS transistors constituting a differential pair of differential amplifiers; 502 and 503 designate PMOS transistors constituting load on the differential amplifiers; 504 designates a bias current source for the differential amplifier; 505 designates a current source for correcting an offset voltage (hereinafter called an “offset voltage correction current source”); INP and INN denote input terminals of the differential amplifier; and OUTP denotes an output terminal of the differential amplifier.
A known differential amplifier is constituted of the NMOS transistors 500 and 501, the PMOS transistors 502 and 503, and the constant current source 504 for biasing purpose. One end of the offset voltage correction current source 505 is connected to a drain of the NMOS transistor 500, and the other end of the same is connected to a power source VDD. The offset voltage correction current source 505 serves as causing an electric current to flow to the drain of the NMOS transistor 500.
The principle of operation for correcting an offset voltage will be described hereunder. In order to facilitate comprehension of a working effect yielded by the principle, the NMOS transistors 500 and 501 and the PMOS transistors 502 and 503 are assumed not to have property variations responsible for an offset voltage.
Under such hypothetical conditions, consideration is first given to a steady state where a single DC bias voltage Vi is applied to both input terminals INP and INN and where the offset voltage correction current source 505 assumes a current value of zero. In this state, provided that an electric current flowing through the NMOS transistor 500 is taken as IA; that an electric current flowing through the NMOS transistor 501 is taken as IB; and a current value of the constant current source 504 is taken as It, we have IA=IB=It/2.
Next, consideration is given to a case where the current value of the offset voltage correction current source 505 is ios. In this case, provided that mutual conductance of the NMOS transistor 500 is taken as gmn, the current ios is added to a steady-state current flowing through the NMOS transistor 500, and an input-equivalent offset voltage vosi (=ViA−ViB) originating from the current ios is expressed byvosi=ios/gmn  (1).
From Expression (1), it is understood that the electric current ios is caused to flow into one of the MOS transistors constituting the differential pair, whereby a voltage vosi is acquired as an input-equivalent offset voltage corresponding to the amount of electric current. Consequently, even when the differential amplifier is not ideal and previously has an offset voltage, the offset voltage can be corrected by adjusting the current ios.
However, according to the offset voltage correction circuit of the related art, a very small current value is required for a correction current, and difficulty is encountered in acquiring such a small current value with accuracy. Therefore, accurate adjustment of the offset voltage cannot be carried out. For instance, when an input-equivalent offset voltage of vosi=50 [μV] is acquired, the current must be set to ios=0.1 [μA] on the assumption that gmn=2 [mS]. When the mutual conductance gm of the NMOS transistors 500 and 501 is much smaller, the correction current must be set to a much smaller value in order to acquire the same input-equivalent offset voltage.
Moreover, when the mutual conductance has changed for reasons of environmental variations such as process variations, there arises a problem of the input-equivalent offset voltage greatly changing according to Expression (1) because the input-equivalent offset voltage exhibits high sensitivity to the mutual conductance.
Incidentally, a class D amplifier for amplifying power by converting an analogue signal, such as a music signal, into a pulse signal has hitherto been known.
FIG. 11 shows a related-art class D amplifier. Analog input signals AIN(+) and AIN(−), which are of opposite polarities, are applied from an external signal source to the input terminals INP and INM. These analog input signals AIN(+) and AIN(−) are input to input terminals T11 and T12 of the class D amplifier by way of capacitors Cin 1 and Cin 2. After having been input to the class D amplifier, the signal is input to and amplified by an input stage amplifying circuit 100, and the thus-amplified signal is input subsequently to an integration circuit 110. A pulse width modulation (PWM) circuit 120 pulse-width modulates a signal output from the integration circuit 110.
An output buffer 1300 outputs complementary pulse signals OUTP and OUTM in accordance with a signal output from the pulse width modulation circuit 120. These pulse signals OUTP and OUTM are returned through feedback to an input side of a differential amplifier 114 constituting the integration circuit 110 by way of feedback resistors R41 and R42, whereby distortion of a waveform of the pulse signal is corrected. The pulse signals OUTP and OUTM are output to the outside by way of output terminals T21 and T22 and pass through a low pass filter consisting of inductors L1, L2 and a capacitor C, to thus become an analog signal used for driving a speaker SP.
Incidentally, a popping sound induced by an offset voltage of the circuit usually arises in an amplifier for audio purpose. Likewise, even in the class D amplifier mentioned above, transistors constituting the differential operational amplifiers 101 and 114 have an offset voltage induced by variations in the process for manufacturing or the like. Even when no signal is input, a mean voltage value of the output pulse signal OUTP and a mean voltage value of the output pulse signal OUTM differ from each other. Specifically, an offset voltage is output.
In this case, since the offset voltage is applied to the speaker at all times, a popping sound is emitted from the speaker at the time of a mute or power shutoff.
In the class D amplifier shown in FIG. 11 (the differential operational amplifiers 101 and 114 do not include the previously-described offset correction circuit of the related art), there may arise a case where a source voltage of an output buffer 1300 differs from a source voltage of the integration circuit 110 and that of the input stage amplification circuit 100. For instance, consideration is given to a case where the former source voltage is 15 V and where the latter source voltage is 3.3 V.
In this case, in relation to the pulse signals OUTP and OUTM output at the time of input of no signal, a rectangular waveform having a duty ratio of 50% is output complementarily. Since the source voltage of the output buffer 1300 is 15 V, a mean voltage of the output pulse signal OUTP and a mean voltage of the output pulse signal OUTM each assume a value of 7.5 V under ideal conditions where no offset voltage exists in the differential operational amplifiers 101 and 114; where a resistance value of input resistance of positive phase side (R31) of the integrator 110 is equal to a resistance value of input resistance of a reversal phase (R32) of the same; and where a resistance value of a positive phase side (R41) of a feedback resistor and a resistance value of a reversal side (R42) of the same are also equal to each other. Therefore, a voltage difference applied across the input terminals of the speaker SP is 0 V, and no sound is emitted.
Mean voltages of the signals SA and SA output from the differential operational amplifier 101 whose source voltage is 3.3 V are 1.65 V, respectively, because the signals SA and SB are positive fed back so as to coincide with a reference voltage that is one half of the source voltage. Accordingly, 5.85 volts corresponding to a voltage difference between a mean value of the output pulse signals OUTP and OUTM and a mean value of the output signals SA and SB is applied to the feedback resistor R41 and an input resistor R31 of the integration circuit 110 and the feedback resistor R42 and an input resistor R32 of the integration circuit 110, respectively. Consequently, an electric current conforming with the sum of a resistance value of the feedback resistor R41 and a resistance value of the input resistor R31 and an electric current conforming with the sum of a resistance value of the feedback resistor R42 and a resistance value of the input resistor R32 flow from the output of the output buffer 1300 to the output of the differential operational amplifier 101.
Consideration is given to a case where a difference attributable to variations exists between the resistance value of the feedback resistor R41 and the resistance value of the feedback resistor R42. Voltages applied to the two inputs of the differential operational amplifier 114 are returned through feedback and hence are equal to each other. Since the differential operational amplifier 114 functions such that the voltage applied across the input resistor R31 and the voltage applied across the input resistor R32 become equal to each other, the electric currents flowing to the respective resistors become equal to each other.
Since the electric currents having the same value flow through the feedback resistors R41 and R42, respectively, a difference arises between a voltage drop of the feedback resistor R41 and a voltage drop of the feedback resistor R42 appears in the output of the output buffer 1300 even when the value of the input resistor R31 and the value of the input resistor R32 are equal to each other. Consequently, an offset voltage conforming with the difference between the resistance value of the feedback resistor R41 and the resistance value of the feedback resistor R42 appears in the output pulse signals OUTP and OUTM.
The offset voltage (a potential difference) in the signals SA and SB caused by the differential operational amplifier 101 is multiplied by an amplification factor (R41/R31) of a negative feedback amplifier consisting of the input resistors R31 and R32, the feedback resistors R41 and R42, the integrator 110, the pulse width modulation circuit 120, and the output buffer 1300, and the thus-amplified voltage appears at the output terminals T21 and T22. For instance, when a ratio of the resistance value R31 to the resistance value R41 is 1:20, the offset voltage having arisen in the signals SA and SB is output while being multiplied by a factor of 20. When a difference exists between the resistance value of the feedback resistor R41 and the resistance value of the feedback resistor R42, this amplification factor varies from the positive phase side to the reversal phase side, so that the offset voltage becomes much greater.
Moreover, even when a difference exists between the resistance value of the input resistor R31 and that of the input resistor R32, the offset voltage arises.
Specifically, the amplification factor (R41/R31) achieved at the positive phase side of the negative feedback amplifier constituting the class D amplifier differs from the amplification factor (R42/R32) achieved at the reversal phase side of the same for reasons of variations in resistance value or the like, the difference appears as an output offset voltage. The speaker SP is activated by the offset voltage, which becomes one cause of emission of a popping sound at the time of a mute or power shutoff.
However, even when the previously-described offset voltage correction circuit of the related art is used to eliminate the offset voltage, the offset voltage of the differential operational amplifier per se can be corrected, but there arises a problem of a failure to correct an offset voltage which arises when an input resistance value or a feedback resistance value of the class D amplifier varies from the positive phase side to the reversal phase side.